The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a kind of transistor that is widely applied in digital circuits and analog circuits. When the gate dielectric layer of a MOSFET is made of a high-k dielectric material, the gate drain current shall be effectively reduced; however, as a high-k gate dielectric layer is formed at first, the molecular structure of the high-k gate dielectric layer probably have defects. In order to remove the defects, it has to be annealed at a high temperature (600° C.-800° C.). Besides, annealing a high-k gate dielectric layer is able to enhance reliability of a transistor. However, a metal silicide layer in the transistor cannot endure the high temperature required for annealing the high-k dielectric layer, wherein the structure of the metal silicide layer is prone to change under the high temperature, such that the resistivity of the metal silicide layer increases, which thereby impedes performance of the transistor.
In the prior art, patent application US2007/0141798A1 provides a method capable of annealing a high-k gate dielectric layer without damaging a metal silicide layer, which comprises following steps:
forming a transistor with a sacrifice gate on a substrate; depositing a first interlayer dielectric layer on the substrate; removing the sacrifice gate to form a gate trench; depositing a high-k dielectric layer in the gate trench; annealing the high-k dielectric layer; depositing a first metal layer in the gate trench; depositing a second interlayer dielectric layer on the first interlayer dielectric layer and the transistor; etching the first interlayer dielectric layer and the second interlayer dielectric layer to a source and a drain to form a first contact trench and a second contact trench respectively; depositing a second metal layer into the first contact trench and the second contact trench; annealing the second metal layer to form a metal silicide layer at the source and the drain; and depositing a third metal layer to fill the first contact trench and the second contact trench.
Since a contact layer (e.g. a metal silicide layer) is formed after the high-k dielectric layer has been annealed, thus the metal silicide layer is prevented from damage under the high temperature.
However, aforesaid method though is able to protect the metal silicide layer from damage arising from annealing of the high-k dielectric layer, limitations of the method lies in that the metal silicide layer is formed nowhere but between the contact trench and the source/drain regions, thus the area of the region covered by metal silicide on the surface of the source/drain regions is limited, thus the contact resistance between the source/drain regions and the metal silicide layer of the transistor cannot be reduced adequately. Therefore, how to reduce the contact resistance between the source/drain regions and the contact layer (e.g. a metal silicide layer) becomes an issue urgent to solve.